A 32-Channel High Resolution Time-to-Digital Converter (TDC) in a Lattice ECP2M Field-Programmable-Gate-Array (FPGA)

The development of the TDC on Xilinx Virtex-4 FPGA [1] has been continued. The dead-time could be decreased to 15 ns by pipelining. In order to test the design in experiments it was moved to the VULOM-4 boards and adapted to triggered systems. Since the differential timing signals were converted to single ended signals on the VULOM-4 board before being fed into the FPGA, a slight decrease in resolution (14 ps RMS) was observed in laboratory measurements between some channels. For this reason a new version of the VULOM-4 board is prepared with shorter single ended signal lines. First detector measurement data were collected with the CBM setup by using 32 channels on two VULOM-4 boards. The analysis of the collected data is still ongoing. In order to explore the consequences of using a different FPGA architecture and thus increasing the knowledge of TDC designs in FPGAs the existing TDC design was adapted to the Lattice ECP2M FPGA. A 32-channel TDC was implemented on a Lattice ECP2M. The fine time interval calculations were achieved by Tapped-Delay-Line method using dedicated carry-chain lines. A Multi-bit adder structure was used in order to form the delay line. Each channel has an individual fine counter, an encoder and a First-In-First-Out memory block (FIFO). A common coarse counter generates time flags for the time information of each conversion. The time-to-digital conversion and the data read-out were undertaken at 200 MHz and 100 MHz clock frequency respectively. The time interval between the rising edge of a trigger signal and the rising edge of the next system clock was measured at the fine counter. The result generated by the fine counter in thermometer code [2] was converted to a binary code in the encoder and stored in the FIFO with a time stamp generated by the common coarse counter as well as a channel number. The data was calibrated offline by using the bin-by-bin calibration method [3]. In our measurements we used two channels in order to measure the time difference between two triggers. The triggers were generated by Tektronix Data Timing Generator DTG5078. Sets of measurements with different time differences were done in order to test the stability and the consistency of the TDC. The time difference was increased logarithmically starting from zero up to one microsecond in order to observe the effects on the measured mean value and RMS. Figure